? semiconductor components industries, llc, 2006 february, 2006 ? rev. 3 1 publication order number: mmbf5484lt1/d mmbf5484lt1 preferred device jfet transistor n?channel features ? pb?free package is available maximum ratings rating symbol value unit drain?gate voltage v dg 25 vdc reverse gate?source voltage v gs(r) 25 vdc forward gate current i g(f) 10 madc continuous device dissipation at or below t c = 25 c linear derating factor p d 200 2.8 mw mw/ c storage channel temperature range t stg ?65 to +150 c thermal characteristics characteristic symbol max unit total device dissipation fr?5 board, (note 1) t a = 25 c derate above 25 c p d 225 1.8 mw mw/ c thermal resistance, junction?to?ambient r ja 556 c/w junction and storage temperature t j , t stg ?55 to +150 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. fr?5 = 1.0 x 0.75 x 0.062 in. http://onsemi.com sot?23 (to?236) case 318 style 10 device package shipping ? ordering information mmbf5484lt1 sot?23 3,000 / tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. MMBF5484LT1G sot?23 (pb?free) 3,000 / tape & ree l preferred devices are recommended choices for future use and best overall value. 1 2 3 *date code orientation and/or overbar may vary depending upon manufacturing location. 1 m6b m m6b = device code m = date code* = pb?free package (note: microdot may be in either location) marking diagram 2 source 3 gate 1 drain
mmbf5484lt1 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min max unit off characteristics gate?source breakdown voltage (i g = ?1.0 adc, v ds = 0) v (br)gss ?25 ? vdc gate reverse current (v gs = ? 20 vdc, v ds = 0) (v gs = ? 20 vdc, v ds = 0, t a = 100 c) i gss ? ? ?1.0 ?0.2 nadc adc gate source cutoff voltage (v ds = 15 vdc, i d = 10 nadc) v gs(off) ?0.3 ?3.0 vdc on characteristics zero?gate?voltage drain current (v ds = 15 vdc, v gs = 0) i dss 1.0 5.0 madc small? signal characteristics forward transfer admittance (v ds = 15 vdc, v gs = 0, f = 1.0 khz) |y fs | 3000 6000 mhos output admittance (v ds = 15 vdc, v gs = 0, f = 1.0 khz) |y os | ? 50 mhos input capacitance (v ds = 15 vdc, v gs = 0, f = 1.0 mhz) c iss ? 5.0 pf reverse transfer capacitance (v ds = 15 vdc, v gs = 0, f = 10 mhz) c rss ? 1.0 pf output capacitance (v ds = 15 vdc, v gs = 0, f = 1.0 mhz) c oss ? 2.0 pf f, frequency (mhz) 30 10 b is @ i dss f, frequency (mhz) 5.0 figure 1. input admittance (y is ) figure 2. reverse transfer admittance (y rs ) common source characteristics admittance parameters (v ds = 15 vdc, t channel = 25 c) f, frequency (mhz) 20 f, frequency (mhz) 10 figure 3. forward transadmittance (y fs ) figure 4. output admittance (y os ) g is , input conductance (mmhos) 20 10 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 20 30 50 70 100 200 300 500 700 1000 b is , input susceptance (mmhos) g fs , forward transconductance (mmhos) |b fs |, forward susceptance (mmhos) g rs , reverse transadmittance (mmhos) b rs , reverse susceptance (mmhos) 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 g os , output admittance (mhos) b os , output susceptance (mhos) 3.0 0.05 0.07 0.1 0.2 0.3 0.7 0.5 1.0 2.0 10 20 30 50 70 100 200 300 500 700 1000 10 20 30 50 70 100 200 300 500 700 1000 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 30 50 70 100 200 300 500 700 1000 b is @ 0.25 i dss g is @ i dss g is @ 0.25 i dss b rs @ i dss 0.25 i dss g rs @ i dss , 0.25 i dss g fs @ i dss |b fs | @ i dss |b fs | @ 0.25 i dss b os @ i dss and 0.25 i dss g os @ i dss g os @ 0.25 i dss g fs @ 0.25 i dss
mmbf5484lt1 http://onsemi.com 3 figure 5. s 11s figure 6. s 12s 0 350 340 330 10 20 30 180 190 200 210 170 160 150 320 310 300 290 280 270 260 250 240 230 220 40 50 60 70 80 90 100 110 120 130 140 0 350 340 330 10 20 30 180 190 200 210 170 160 150 320 310 300 290 280 270 260 250 240 230 220 40 50 60 70 80 90 100 110 120 130 140 0 350 340 330 10 20 30 180 190 200 210 170 160 150 320 310 300 290 280 270 260 250 240 230 220 40 50 60 70 80 90 100 110 120 130 140 0 350 340 330 10 20 30 180 190 200 210 170 160 150 320 310 300 290 280 270 260 250 240 230 220 40 50 60 70 80 90 100 110 120 130 140 1.0 0.9 0.8 0.7 0.6 0.4 0.3 0.2 0.1 0.0 1.0 0.9 0.8 0.7 0.6 0.6 0.5 0.4 0.3 0.3 0.4 0.5 0.6 900 900 800 700 600 500 400 300 200 100 800 700 600 500 400 300 200 100 i d = 0.25 i dss i d = i dss 100 200 300 400 600 700 800 900 500 i d = i dss , 0.25 i dss 900 500 800 700 600 500 400 300 200 100 i d = 0.25 i dss i d = i dss 100 200 300 400 900 600 700 800 900 800 600 400 300 200 200 100 i d = 0.25 i dss i d = i dss 900 100 500 700 300 400 500 600 700 800 figure 7. s 21s figure 8. s 22s common source characteristics s?parameters (v ds = 15 vdc, t channel = 25 c, data points in mhz)
mmbf5484lt1 http://onsemi.com 4 f, frequency (mhz) 10 g ig @ i dss f, frequency (mhz) 0.5 figure 9. input admittance (y ig ) figure 10. reverse transfer admittance (y rg ) common gate characteristics admittance parameters (v dg = 15 vdc, t channel = 25 c) f, frequency (mhz) f, frequency (mhz) figure 11. forward transfer admittance (y fg ) figure 12. output admittance (y og ) g ig , input conductance (mmhos) 20 10 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 20 30 50 70 100 200 300 500 700 1000 b ig , input susceptance (mmhos) g fg , forward transconductance (mmhos) b fg , forward susceptance (mmhos) g rg , reverse transadmittance (mmhos) b rg , reverse susceptance (mmhos) 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 g og , output admittance (mmhos) b og , output susceptance (mmhos) 0.3 0.01 0.1 0.2 10 20 30 50 70 100 200 300 500 700 1000 10 20 30 50 70 100 200 300 500 700 1000 0.01 0.02 0.03 0.3 10 20 30 50 70 100 200 300 500 700 1000 b ig @ 0.25 i dss b ig @ i dss g rg @ 0.25 i dss g fg @ i dss g fg @ 0.25 i dss b rg @ 0.25 i dss b og @ i dss , 0.25 i dss g og @ i dss g og @ 0.25 i dss 0.2 0.005 0.007 0.02 0.03 0.05 0.07 0.1 0.05 0.07 0.1 0.2 0.5 0.7 1.0 b rg @ i dss 0.25 i dss g ig @ i dss , 0.25 i dss b fg @ i dss
mmbf5484lt1 http://onsemi.com 5 0 350 340 330 10 20 30 180 190 200 210 170 160 150 320 310 300 290 280 270 260 250 240 230 220 40 50 60 70 80 90 100 110 120 130 140 0 350 340 330 10 20 30 180 190 200 210 170 160 150 320 310 300 290 280 270 260 250 240 230 220 40 50 60 70 80 90 100 110 120 130 140 0 350 340 330 10 20 30 180 190 200 210 170 160 150 320 310 300 290 280 270 260 250 240 230 220 40 50 60 70 80 90 100 110 120 130 140 0 350 340 330 10 20 30 180 190 200 210 170 160 150 320 310 300 290 280 270 260 250 240 230 220 40 50 60 70 80 90 100 110 120 130 140 figure 13. s 11g figure 14. s 12g figure 15. s 21g figure 16. s 22g 0.7 0.6 0.5 0.4 0.3 0.04 0.5 0.4 0.3 0.2 1.0 0.9 0.8 0.7 0.6 0.03 0.02 0.01 0.0 0.01 0.02 0.03 0.04 0.1 900 900 800 700 600 500 300 200 100 800 700 600 500 400 300 200 100 i d = 0.25 i dss i d = i dss 100 200 300 400 500 600 700 800 900 900 600 700 800 i d = 0.25 i dss i d = i dss 100 900 100 900 i d = 0.25 i dss i d = i dss 1.5 100 400 500 600 700 800 900 i d = i dss , 0.25 i dss common gate characteristics s?parameters (v ds = 15 vdc, t channel = 25 c, data points in mhz)
mmbf5484lt1 http://onsemi.com 6 package dimensions sot?23 (to?236) case 318?08 issue an d a1 3 12 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. 318?01 thru ?07 and ?09 obsolete, new standard 318?08. mm inches scale 10:1 0.8 0.031 0.9 0.035 0.95 0.037 0.95 0.037 2.0 0.079 view c l 0.25 l1 e e e b a see view c dim a min nom max min millimeters 0.89 1.00 1.11 0.035 inches a1 0.01 0.06 0.10 0.001 b 0.37 0.44 0.50 0.015 c 0.09 0.13 0.18 0.003 d 2.80 2.90 3.04 0.110 e 1.20 1.30 1.40 0.047 e 1.78 1.90 2.04 0.070 l 0.10 0.20 0.30 0.004 0.040 0.044 0.002 0.004 0.018 0.020 0.005 0.007 0.114 0.120 0.051 0.055 0.075 0.081 0.008 0.012 nom max l1 h 2.10 2.40 2.64 0.083 0.094 0.104 h e 0.35 0.54 0.69 0.014 0.021 0.029 c *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* style 10: pin 1. drain 2. source 3. gate on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mmbf5484lt1/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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